Industrial demand requires IC circuits to have a higher density so as to reduce the size of the MOS transistor. However, the reduction of the size of the MOS transistor results in the emergence of the two well-known parasitic effects, i.e., short channel effect emerging as a result of the reduction of the gate length and drain induced barrier lowering effect, which may easily deteriorate electrical properties of the device, such as reduction of the gate threshold voltage, increase in power consumption, and signal-to-noise ratio (SNR) decline. Physically, the above effects can be explained as follows: when the transistor is turned off (the gate voltage is zero), static electricity impact of the source/drain region in a very small device or voltage applied to the drain electrode on the channel region reduces the energy barrier of electrons or holes in the channel, and results in a higher turn-off current.
In order to control the short channel effect, more impurity elements such as phosphorus, boron and the like have to be doped in the channel, which may easily lead to the reduction of the mobility of carries in the device channel. Moreover, the distribution used to dope dopants into the channel can hardly control the problem of steepness, which may easily result in severe short channel effects. The thickness of gate oxides will also encounter a bottleneck problem of development, the thinning rate in the gate oxide thickness can hardly keep up with the reducing pace of the gate width, and gate dielectric leakage is increasing; critical dimensions continue to shrink, which may easily cause the resistance of the source/region to increase continuously and the power consumption of the device to become greater.
Strained silicon technology can control short channel effects effectively. Strained silicon has been used as an MOS transistor of a substrate, which uses the different characteristics of the lattice constant of silicon germanium from monocrystalline silicon to make the epitaxial layer of silicon germanium produce structural strain so as to form strained silicon. Since the lattice constant of the SiGe layer is greater than that of silicon, mechanical stress is generated in the channel region, which causes changes of carrier mobility. In FET, tensile stress can increase electron mobility and reduce hole mobility, and can advantageously improve the performance of NMOS devices; while compressive stress can increase hole mobility and reduce electron mobility, and can advantageously improve the performance of PMOS devices.
However, the traditional silicon germanium strained silicon technology also begins to face bottlenecks, which can hardly provide stronger strain to the channel and cannot effectively enhance the performance of the semiconductor device.